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Audio Controllers
ML675200/ML67Q5200 Digital Audio Controller
Description
The Oki ML675200 and ML67Q5200 Application Specific Standard Products (ASSP) devices are targeted at the growing market for applications using the MP3 audio processing compression protocol. Available in two versions, ROM-less or Flash ROM, the ML675200 and ML67Q5200 devices incorporate an advanced dual processor core architecture featuring an ARM7TDMITM 32-bit RISC CPU core and a TeakTM 16-bit DSP core. The CPU-DSP architecture offers system developers both performance and flexibility. The ARM7TDMI RISC core provides 32-bit performance for application level software with access to general purpose I/O. The DSP core offers the numerical processing power dedicated to repetitive tasks such as MP3 encoding/decoding. In addition to the two processor cores, the ML675200 and ML67Q5200 devices offer a wide variety of integrated peripherals, allowing system designers to implement a complete MP3 system requiring minimum external devices. Among these useful features are a USB 1.1 device controller, 32 Kbytes of SRAM, serial UART ports, GPIO, timers, and analog channels. Other powerful features include a 4-channel DMA controller for efficient data movement, a PLL circuit, a builtin controller for external memory, and a built-in voice Codec.
Features
* * * * * ARM7TDMI 32-bit RISC CPU 30 MHz CPU frequency, 60 MHz DSP frequency 256 Kbyte internal Flash ROM (ML67Q5200) 32 Kbyte internal RAM Audio Codec: MP3 encoder/decoder * Voice Codec: 4-bit ADPCM2 * 4-channel DMA controller * 4-channel A/D converter
* USB controller (version 1.1)
Applications
* Digital audio players (Portable MP3/WMA player, etc.) * Educational toys * Personal Digital Assistants (PDA) * Home audio systems
ML675200/Q5200 Digital Audio Controllers
Part Number ML675200-LA ML67Q5200-NLA Clock Frequency 30 MHz CPU, 60 MHz DSP 30 MHz CPU, 60 MHz DSP Built-in Flash Size None (External Max 1 Mbyte) 256 KB Packages 144-pin plastic LFBGA (P-LFBGA144-1111-0.80) 144-pin plastic LFBGA (P-LFBGA144-1111-0.80)
ML675200/ML67Q5200
Block Diagram
External Bus I/F XD[15:0] XOE_N XA[19:1] XWE_N ROMCS_N XBS0_N RAMCS_N XBS1_N IOCS_N
Flash ROM and/or RAM
SDRAM
SRAM
I/O
CPU (PLAT-7D) TCKA TMSA TRSTA_N TDIA TDOA ARM7TDMI Memory Controller TIC Unified Cache Cache Cont. AHB Bridge MUX Flash ROM 256 kB[1]
SDRAM Contr. AMBA AHB
RAM 32 Kb AHB I/F Dual Port RAM 2.25kB ZRAM 8kW Dual Port RAM 2.25kB BIU Boot ROM P-Bus ZRAM 8kW DSP Module
AHB/APB Bridge
Arbiter AMBA APB Bus
Interrupt Controller
Extended Interrupt Cont. DMA Controller 4ch
AHB APB Bridge
Expanded Peripheral Bus (AMBA APB)
System TIMER
UART
System Controller
TXD0 RXD0 OSC0 OSC1_N OSC2 OSC3_N EXINT0 EXINT1 EXINT3 CLKG
Z-Bus PRAM 32kW
OCEM CLKG JAM JTAG XRAM 8kW X-Bus XRAM 8kW YRAM 8kW Y-Bus YRAM 8kW TCKT TMST TDIT TINTP TDOT
Teak DSP Core NAND Flash Memory Data Transfer Buffer 512B x 4 16-bit Auto-Reload Timer 3ch EZ-Bus USB Device Controller NAND Flash Mem. Contr I2C 1ch Clock Sync. 2ch 16-bit PWM 1ch 8-bit ADC 4ch PCM Buffer 9kB SAI trans. RSTGEN
ICU
DSPOUT0 DSPOUT1
CGCON
WDT / Reset
SIO Buffer 64B SAI Recv.
DDSPTXD
CGCON
GPIO
PC I/F VBUSIN PUCTL D+ D-
NAND Flash Memory I/F FD[7:0] FRD_N FWR_N FCLE FALE FRB
User I/F SDAT SCL
User I/F TXD1 RXD1 SIOCK1 TXD2 RXD2 SIOCK2
User I/F PortA PortB PortC PortD PortE
User I/F PWMOUT
User I/F AIN[3:0]
DAC I/F CKOUTD SDD WSD SCLD
ADC I/F CKOUTA SDA WSA SCLA
1. ML67Q5200 only. The Ml675200 does not contain a built-in Flash ROM.
2 * Oki Semiconductor
ML675200/ML67Q5200
Functional Description
High-Performance ARM-based CPU
* Instructions: ARM (32-bit length) and Thumb (16-bit length) can be mixed. * General register bank: 31 x 32 bits * Built-in barrel shifter: ALU and barrel shift operations can be executed by one instruction. * Multiplier: 32 bits x 8 bits (Modified Booth Algorithm) * Cache: 8 Kbyte, 4-way copy back unified cache * Built-in debug function: JTAG interface * STOP mode: Stops the DSP module clock first, then the clock for the entire device. * SLEEP mode: Stops the power supply to the DSP module first, then stops the clock for the entire device.
DSP Module
The Teak DSP decodes MP3/WMA digital audio data. Also encodes/decodes voice data as Oki ADPCM.
* * * * * *
X-RAM: 16 Kwords (32 Kbytes) Y-RAM: 16Kwords (32 Kbytes) Z-RAM: 16 Kwords (32 Kbytes) P-program RAM: 32 Kwords (64 Kbytes) Built-in debug function: JTAG interface MP3 decoder:
- MPEG-1 layer3, MPEG-2 layer3, MPEG-2.5
* WMA decoder:
- Bit rate: 64 kbps, 96 kbps, 128 kbps, 160 kbps, 192 kbps - Sampling rate: 32 kHz, 44.1 kHz, 48 kHz
* MP3 encoder:
- 64 kbps/96 kbps/128 kbps @ 44.1kHz
USB Control
The USB controller is compliant with the USB specification (version 1.1) and can transfer data at 12 Mbps. The controller has 6 types of endpoints for control/bulk/isochronous/interrupt transfers.
NAND Flash Memory Control
The NAND Flash memory circuit automatically reads data from and writes data to an external 528-byte NAND Flash Memory. Also includes an ECC circuit that detects and corrects multiple-bit data errors.
DMA Control
The 4-channel DMA controller transfers data between:
* Memory and memory * I/O and memory * I/O and I/O
External Memory Control
The external memory controller provides access to externally-connected devices such as ROM (FLASH), SRAM, SDRAM and I/O. Connect 16-bit data bus length device and byte unit access device which have byte select function.
Power Management
The HALT, STOP, and SLEEP functions are supported as power-save functions. Switching the CPU clock to the 1/2, 1/4, or 1/8 of the main clock enables operation in a low power consumption mode.
* HALT mode: Stops the ARM7TDMI and AHB/APB bus.
Oki Semiconductor * 3
ML675200/ML67Q5200
Pin Configuration
NC AIN3 PIOD9/ EXINT2 VDD_IO GND PIOD5/ TXD0 PIOD2/ SDA WSD GND VDD_IO GND VDD_IO VDD_ CORE TEST0 NC N
AIN2
AGND
PIOD4/ SCLA PIOD7/ EXINT0 PIOD8/ EXINT1 SDRAM MOD PIOE1/ FD1 PIOE2/ FD2 PIOE6/ FD6 PIOE10/ FCLE VBUS
PIOD1/ PIOD0/ DSPOUT CKOUTA PWMOUT 1 PIOD6/ RXD0 PIOD3/ WSA SCLD SDD
VDD_ CORE DSPOUT 0 DSPTXD
GND
OSC3_N
OSC1_N
TEST1
M
AIN0
TCKT
AIN1
OSC2
OSC0
GND
GND
TEST2
L
TMST
TINTP
AVDD
VDD_ CORE
CKOUTD
VDD_ CORE
RES_N
PIOD14/ RXD2 PIOC13/ TXD2 VDD_IO
PIOD11/ RXD1 PIOC8/ XBS0_N VDD_ CORE PIOC4/ RAMCS_ N PIOC1/ XA18 GND
PIOD15/ SIOCK2 PIOC12/ SIOCK1 PIOC9/ XBS1_N PIOC7/ XWE_N PIOC0/ XA17 PIOB14/ XA15 PIOB11/ XA12 PIOB8/ XA9 PIOB6/ XA7 NC
K
TDOT
GND
TDIT
PIOC10/ TXD1 GND
J
VDD_ CORE PIOE4/ FD4 PIOE9/ FWR_N PIOE12/ FRB PIOE14/ SCL PUCTL
PIOE0/ FD0 GND
VDD_IO
H
PIOE3/ FD3 PIOE5/ FD5 VDD_IO
144-Pin LFBGA (TOP VIEW)
PIOC5/ IOCS_N PIOC2/ XA19 PIOB15/ XA16
PIOC6/ XOE_N PIOC3/ ROMCS _N PIOB12/ XA13 PIOB9/ XA10 PIOB7/ XA8 PIOB1/ XA2 PIOB3/ XA4 3
G
PIOE7/ FD7 PIOE8/ FRD_N PIOE11/ FALE PIOE15/ VBUSIN D-
F
E
PIOE13/ SDAT TCKA
GND
PIOA5/ XD5 PIOA6/ XD6 PIOA4/ XD4 PIOA3/ XD3 8
PIOA8/ XD8 PIOA9/ XD9 PIOA7/ XD7 PIOA10/ XD10 7
GND
PIOA14/ XD14 GND
PIOB2/ XA3 VDD_ CORE PIOA15/ XD15 PIOB0/ XA1 4
PIOB13/ XA14 PIOB10/ XA11 PIOB4/ XA5 PIOB5/ XA6 2
D
TRSTA_ N PIOA1/ XD1 TDOA
PIOA0/ XD0 PIOA2/ XD2 VDD_IO
VDD_IO
C
D+
TDIA
PIOA11/ XD11 PIOA13/ XD13 6
PIOA12/ XD12 VDD_IO
B
NC
GND
TMSA
A
13
12
11
10
9
5
1
Figure 1. 144-Pin LFBGA
Notes: 1. For pins that have multiple functions, the signals are noted by their primary / secondary functions. 2. Leave NC pins unconnected.
4 * Oki Semiconductor
ML675200/ML67Q5200
Pin Descriptions
In the Type column, an "I" indicates the signal is an input, an "O" indicates the signal is an output, and an "I/O" indicates the signal is bi-directional. Signals with a "_N" suffix are active low.
Pin Descriptions
Primary Function Classification Port Symbol PIOA0 PIOA1 PIOA2 PIOA3 PIOA4 PIOA5 PIOA6 PIOA7 PIOA8 PIOA9 PIOA10 PIOA11 PIOA12 PIOA13 PIOA14 PIOA15 Port PIOB0 PIOB1 PIOB2 PIOB3 PIOB4 PIOB5 PIOB6 PIOB7 PIOB8 PIOB9 PIOB10 PIOB11 PIOB12 PIOB13 PIOB14 PIOB15 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 16-bit I/O port B. 16-bit I/O port A. Description Symbol XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 XD8 XD9 XD10 XD11 XD12 XD13 XD14 XD15 XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XA9 XA10 XA11 XA12 XA13 XA14 XA15 XA16 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O External access address output port. Secondary Function Description External access data I/O port.
Oki Semiconductor * 5
ML675200/ML67Q5200
Pin Descriptions
Primary Function Classification Port Symbol PIOC0 PIOC1 PIOC2 PIOC3 PIOC4 PIOC5 PIOC6 PIOC7 PIOC8 PIOC9 PIOC10 PIOC11 PIOC12 PIOC13 PIOC14 PIOC15 Port PIOD0 PIOD1 PIOD2 PIOD3 PIOD4 PIOD5 PIOD6 PIOD7 PIOD8 PIOD9 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 10-bit I/O port D. 16-bit I/O port C. Description Symbol XA17 XA18 XA19 ROMCS_N RAMCS_N IOCS_N XOE_N XWE_N XBS0_N XBS1_N TXD1 RXD1 SIOCK1 TXD2 RXD2 SIOCK2 PWMOUT CKOUTA SDA WSA SCLA TXD0 RXD0 EXINT0 EXINT1 EXINT2 Type O O O O O O O O O O O I I/O O I I/O O O I O O O I I I I External ROM chip select output pin. External RAM chip select output pin. External I/O chip select output pin. External access read strobe output pin. External access write strobe output pin. External access byte select (LSB) output pin. External access byte select (MSB) output pin. SIO1 transmit data output pin. SIO1 receive data input pin. SIO1 clock I/O pin. SIO2 transmit data output pin. SIO2 receive data input pin. SIO2 clock I/O pin. PWM output pin. External ADC interface system clock output pin. External ADC interface serial data input pin. External ADC interface channel select signal output pin. External ADC interface serial clock output pin. SIO0 transmit data output pin. SIO0 receive data input pin. External interrupt 0 input pin. External interrupt 1 input pin. External interrupt 2 input pin. Secondary Function Description External access address output port.
6 * Oki Semiconductor
ML675200/ML67Q5200
Pin Descriptions
Primary Function Classification Port Symbol PIOE0 PIOE1 PIOE2 PIOE3 PIOE4 PIOE5 PIOE6 PIOE7 PIOE8 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O 16-bit I/O port E. Description Symbol FD0/CAS_N FD1/RAS_N FD2/SDCLK FD3/SDCS_N FD4/SDCKE FD5/DQM0 FD6/DQM1 FD7/PIOE7 FRD_N Type Secondary Function Description (SDRAMMOD = "H" level) SDRAM control signal output port.
I/O or O (SDRAMMOD = "H" level) I/O or O NAND flash memory I/O or O access data I/O port. I/O or O I/O or O I/O or O I/O or O I/O O NAND flash memory access read strobe output pin. NAND flash memory access write strobe output pin. NAND flash memory access command latch enable output pin. NAND flash memory access address latch enable output pin. NAND flash memory access Ready/Busy Input pin. I2C data I/O pin. I2C clock output pin.
Prohibit setting. Prohibit setting
PIOE9
I/O
FWR_N
O
Prohibit setting.
PIOE10
I/O
FCLE
O
Prohibit setting.
PIOE11
I/O
FALE
O
Prohibit setting.
PIOE12
I/O
FRB
I
Prohibit setting
PIOE13 PIOE14 PIOE15 DAC I/F CKOUTD SDD WSD SCLD DSP port DSPOUT0 DSPOUT1 DSPTXD A/D port AVDD AIN0 to AIN3 AGND USB I/F D+ DPUCTL Reset RES_N
I/O I/O I/O O O O O O O O VDD I GND I/O I/O O I External DAC interface system clock output pin. External DAC interface serial data input pin. External DAC interface channel select signal output pin. External DAC interface serial clock output pin. DSP external control output pin. DSP external control output pin. DSP debug serial data output pin. Analog reference voltage input pin (Connect to the VDD pin when the A/D converter is not used). A/D converter analog input port (Connect to the AVDD or AGND pin when the A/D converter is not used). Analog GND pin (Connect to the GND pin when the A/D converter is not used). USB D+ pin. USB D- pin. External control output pin. Reset input pin.
SDAT SCL VBUSIN
I/O O I
Vbus detect external interrupt input pin.
Oki Semiconductor * 7
ML675200/ML67Q5200
Pin Descriptions
Primary Function Classification Oscillation Symbol OSC0 Type I Description Main clock oscillator input pin. Connect to a crystal or ceramic oscillator of f = 8 MHz. When an external clock is used, this pin is configured as the clock input. Main clock oscillator output pin. Connect to a crystal or ceramic oscillator of f = 8 MHz. The clock output is opposite in phase to OSC0. Leave this pin unconnected when an external clock is used. Audio clock oscillator input pin. Connect to a crystal or ceramic oscillator of f = 16.9344/ 11.2896 MHz. When an external clock is used, this pin is configured as the clock input. Audio clock oscillator output pin. Connect to a crystal or ceramic oscillator of f = 16.9344/ 11.2896 MHz. The clock output is opposite in phase to OSC2. Leave this pin unconnected when an external clock is used. ARM JTAG clock input pin. Leave this pin unconnected for normal operation. ARM JTAG mode select input pin. Leave this pin unconnected for normal operation. ARM JTAG reset input pin. Leave this pin unconnected for normal operation. ARM JTAG data input pin. Leave this pin unconnected for normal operation. ARM JTAG data output pin. Leave this pin unconnected for normal operation. Teak-DSP JTAG clock input pin. Leave this pin unconnected for normal operation. Teak-DSP JTAG mode select input pin. Leave this pin unconnected for normal operation. Teak-DSP JTAG data input pin. Leave this pin unconnected for normal operation. Teak-DSP JAM interrupt output pin. Leave this pin unconnected for normal operation. Teak-DSP JTAG data output pin. Leave this pin unconnected for normal operation. Core power supply pin. Connect all the VDD_CORE pins. IO power supply pin. Connect all the VDD_IO pins. USB power supply pin (Vbus input pin). CORE and I/O GND pin. Test pin. Connect to GND pin for normal operation. Test pin. Connect to VDD_IO pin for normal operation. Test pin. Leave this pin unconnected for normal operation. When this pin is "L" level, the NAND Flash memory interface is enabled. When this pin is "H" level, the SDRAM interface is enabled. This pin must not change state when power is supplied. Symbol Type Secondary Function Description
OSC1_N
O
OSC2
I
OSC3_N
O
CPU JTAG
TCKA TMSA TRSTA_N TDIA TDOA
I I I I O I I I O O VDD VDD VDD GND I I I I
DSP JTAG
TCKT TMST TDIT TINTP TDOT
Power supply [1] VDD_CORE VDD_IO VBUS GND Others TEST0 TEST1 TEST2 SDRAMMOD
1.
Connect all VDD_IO pins, all VDD_CORE pins, and all GND pins. If a device has one or more unconnected VDD_IO, VDD_CORE, or GND pins, proper device operation is not guaranteed.
8 * Oki Semiconductor
ML675200/ML67Q5200
Electrical Characteristics
Absolute Maximum Ratings [1]
Parameter Power supply voltage Power supply for internal cell Power supply for I/O circuit Analog power supply for A/D converter Power supply for USB bus Input voltage Output Current Power dissipation Storage temperature
1.
Symbol VDD_CORE VDD_IO AVDD VBUS VI IO PD TSTG 4 mA buffer
Conditions Tj = 25C Reference GND = 0 V
Rating -0.3 to +2.5 -0.3 to +4.5 -0.3 to +4.5 -0.3 to +4.5 -0.3 to VDD_IO+0.3 16 595 -55 to +150
Unit V
V mA mW C
Ta = 70C per package --
These are maximum ratings not for general operation. Exceeding these maximum ratings could cause damage or lead to permanent deterioration of the device.
Recommended Operating Conditions
(GND = 0 V) Item Digital power supply voltage (core) Digital power supply voltage (I/O) Analog power supply voltage (A/D) Analog power supply voltage (USB) Analog input voltage Operating frequency Symbol VDD_CORE VDD_IO AVDD VBUS VAI fOSC0 fOSC2 Ambient temperature Ta 256 x fs 384 x fs -- During writing to flash ROM Conditions Minimum 1.65 2.70 2.70 3.00 0 - - - -30 0 Typical 1.80 3.00 3.00 3.30 - 8.00 11.2896 16.9344 +25 +25 Maximum 1.95 3.60 3.60 3.60 AVDD - - - +70 +70 C V MHz Unit V
Oki Semiconductor * 9
ML675200/ML67Q5200
DC Characteristics
(VDD_CORE = 2.25 to 2.75V, VDD_IO = 3.0 to 3.6V, Ta = -40 to +85C) Item High level input voltage Low level input voltage Schmitt input buffer threshold voltage Symbol VIH VIL VT+ VTVHYS High level output voltage VOH VOL IIH IIL IOZH IOZL
1. 2. 3. 4. 5. 6. 7.
Conditions TTL Input
Minimum 2.2 -0.3
Typical -- -- 1.5 1.0 0.4 -- -- -- -- -- 66 -- 66 -- --
Maximum VDD_IO+0.3 0.8 2.2 -- -- -- -- 0.2 0.4 10 200 -- -10 20 --
Unit V
[1]
Notes
TTL Input
-- 0.6
V
[2]
VT+ - VTIOH = -100 A IOH = -4 mA IOL = 100 A IOL = 4 mA VIH = VDD_IO VIH = VDD_IO (50 k pull-down) VIL = GND VIL = GND (50 k pull-up) VOH = VDD_IO VOL = GND
-- VDD-0.2 2.2 -- -- -- 10 -10 -200 -- -20
V
[3]
Low level output voltage
V
[4] [5]
High level input current
A
Low level input current
A
[4] [6]
3-State output leakage current
A
[7]
Applicable to the TEST0 to TEST2 pins, SDRAMMOD pin and the JTAG input pins. Applicable to the RES_N pin when inputting to the PIOA to PIOE ports. Applicable when outputting from the PIOA to PIOE ports. Applicable to the CKOUTD/SDD/WSD/SCLD pins, DSPOUT1/DSPOUT0 pins and DSPTXD pin. Applicable to the JTAG output pins (TDOA, TDOT, and TINTP). Applicable to the TEST0/TEST1 pins and SDRAMMOD pin. Applicable to the pull-down pins (TEST2 pin and TCKA/NTRSTA/TCKT pins of JTAG). Applicable to the pull-up pins (RES_N pin and TMSA/TDIA/TMST/TDIT pins of JTAG). Applicable when inputting to the input-output pins (PIOA to PIOE ports).
10 * Oki Semiconductor
ML675200/ML67Q5200
AC Characteristics
External RAM/RAM Read Cycle [1]
(VDD_CORE = 1.65 V to 1.95 V, VDD_IO = 2.7 V to 3.6 V, TA = -30C to +70C) Parameter ROMCS_N setup time RAMCS_N setup time ROMCS_N output hold time 1 RAMCS_N output hold time 1 XA[19:1] setup time XA[19:1] hold time 1 XBS_N[1:0] setup time XBS_N[1:0] hold time 1 XOE_N pulse width XD[15:0] input setup time XD[15:0] input hold time
1.
Symbol tXROMCS tXRAMCS tXROMCSH1 tXRAMCSH1 tXAS tXAH1 tXBS tXBH1 tXOEW tXDIS tXDIH
Condition CL = 50 pF
Min (n0+n1)Tc - 10 (n0+n1)Tc - 10 Tc Tc (n0+n1)Tc - 10 -5 (n0+n1)Tc - 10 -5 n1Tc - 10 40 0
Typ -- -- -- -- -- -- -- -- -- -- --
Max -- -- -- -- -- -- -- -- -- -- --
Units ns ns ns ns ns ns ns ns ns ns ns
n0 = address setup time, n1 = XOE_N/XWE_N pulse width, Tc = HCLK cycle. Address setup time and XOE_N/XWE_N pulse width are parameters that can be set by the ROMAC/RAMAC registers.
tXROMCS, tXRAMCS ROMCS_N/PIOC[3] RAMCS_N/PIOC[4] tXAH2 tXAS XA[19:1]/PIOC[2:0] PIOB[15:0] tXBS XBS_N[1:0]/PIOC[9:8] tBH1
tXROMCSH1, tXRAMCSH1
XOE_N/PIOC[6]
tXOEW
tXDIS XD[15:0]/PIOA[15:0]
tXDIH
Figure 2. External ROM/RAM Read Cycle Timing
Oki Semiconductor * 11
ML675200/ML67Q5200
External RAM/RAM Write Cycle [1]
(VDD_CORE = 1.65 V to 1.95 V, VDD_IO = 2.7 V to 3.6 V, TA = -30C to +70C) Parameter ROMCS_N pulse width RAMCS_N pulse width ROMCS_N output hold time 2 RAMCS_N output hold time 2 XA[19:1] hold time 2 XBS_N[1:0] hold time 2 XWE_N output delay time XWE_N output delay time pulse width XD[15:0] output delay time XD[15:0] output hold time
1. 2.
Symbol tXROMCSW tXRAMCSW tXROMCSH2 tXRAMCSH2 tXAH2 tXBH2 tXWED [2] tXWEW tXDOD [2] tXDOH
Condition CL = 50 pF
Min (n0+n1+1)Tc - 10 (n0+n1+1)Tc - 10 Tc Tc -5 -5 n0Tc - 10 n1Tc - 10 -- Tc - 5
Typ -- -- -- -- -- -- -- -- -- --
Max -- -- -- -- -- -- -- -- n0Tc + 10 --
Units ns ns ns ns ns ns ns ns ns ns
n0 = address setup time, n1 = XOE_N/XWE_N pulse width, Tc = HCLK cycle. Address setup time and XOE_N/XWE_N pulse width are parameters that can be set by the ROMAC/RAMAC registers. tXDOD and tXWED are defined as a time period that starts from the point of change in ROMCS_N/RAMCS_N, XA[19:0], or XBS_N[1:0], whichever signal changes last.
tXROMCSW, tXRAMCSW tXROMCSH2, tXRAMCSH2 ROMCS_N/PIOC[3] RAMCS_N/PIOC[4] tXAH2 XA[19:1]/PIOC[2:0] PIOB[15:0] tBH2 XBS_N[1:0]/PIOC[9:8]
tXWED XWE_N/PIOC[7]
tXWEW
tXDOD XD[15:0]/PIOA[15:0]
tXDOH
Figure 3. External ROM/RAM Write Cycle Timing
12 * Oki Semiconductor
ML675200/ML67Q5200
External SDRAM Bus Timing [1]
(VDD_CORE = 1.65 V to 1.95 V, VDD_IO = 2.7 V to 3.6 V, TA = -30C to +70C) Parameter SDCKE output delay time XA[19:1] output delay time SDCS_N "L" output delay time RAS_N "L" output delay time RAS_N "H" output delay time CAS_N "L" output delay time CAS_N "H" output delay time RAS/CAS minimum delay time RAS active time RAS precharge time XWE_N "L" output delay time XWE_N "H" output delay time DQM[1]/DQM[0] "L" output delay time DQM[1]/DQM[0] "H" output delay time XD[15:0] input setup time XD[15:0] input hold time XD[15:0] output delay time XD[15:0] output hold time
1.
Symbol tSDCKED tSDXAD tSDCSLD tSDRASLD tSDRALHD tSDCASLD tSDCALHD tSDRCD tSDRAS tSDRP tSDWELD tSDWEHD tDOMD tDOMD tSDXDIS tSDXDIH tSDXDOD tSDXDOH
Condition CL = 50 pF
Min 0 -5 -10 -10 -10 -10 -10 nSD1Tc nSD2Tc nSD3Tc -10 -10 -10 -10 15 0 -10 -10
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max 10 10 10 10 10 10 10 -- -- -- 10 10 10 10 -- -- 10 --
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
nSD1 = tRCD, nSD2 = tRAS, nSD3 = tRP. tRCD, tRAS, and tRP are parameters that can be set by the DRPC register. Refer to the User's Manual for more information on these timings.
Oki Semiconductor * 13
ML675200/ML67Q5200
SDCLK/PIOE[2]
tSDCKED SDCKE/PIOE[4]
tSDXAD XA[19:1]/PIOC[2:0] PIOB[15:0] tSDCSD SDCS_N/PIOE[3] tSDRASHD tSDRASLD RAS_N/PIOE[1] tSDRCD tSDCASLD CAS_N/PIOE[0] tSDRAS tSDRP
tSDCASHD
tSDWELD XWE_N/PIOC[7]
tSDDOMLD DQM[1:0]/PIOE[6:5]
tSDDQMHD
tSDXDIS XD[15:0]/PIOA[15:0]
tSDCSIH
Figure 4. SDRAM Read Cycle Timing
14 * Oki Semiconductor
ML675200/ML67Q5200
SDCLK/PIOE[2]
tSDCKED SDCKE/PIOE[4]
tSDXAD XA[19:1]/PIOC[2:0] PIOB[15:0] tSDCSD SDCS_N/PIOE[3] tSDRASHD tSDRASLD RAS_N/PIOE[1] tSDRCD tSDCASLD CAS_N/PIOE[0] tSDRAS tSDRP
tSDCASHD
tSDWELD XWE_N/PIOC[7]
tSDWEHD
tSDDQMLD DQM[1:0]/PIOE[6:5]
tSDDQMHD
tSDXDOS XD[15:0]/PIOA[15:0]
tSDCSOH
Figure 5. SDRAM Write Cycle Timing
Oki Semiconductor * 15
ML675200/ML67Q5200
External I/O Bus Read Cycle [1]
(VDD_CORE = 1.65 V to 1.95 V, VDD_IO = 2.7 V to 3.6 V, TA = -30C to +70C) Parameter IOCS_N setup time IOCS_N output hold time 1 XA[19:1] setup time XA[19:1] hold time 1 XBS_N[1:0] setup time XBS_N[1:0] hold time 1 XOE_N output delay time XOE_N pulse width XD[15:0] input setup time XD[15:0] input hold time
1.
Symbol tXIOCS tXIOCSH1 tXIOAS tXIOAH1 tXIOBS tXIOBH1 tXIOOED tXIOOEW tXIODIS tXIODIH
Condition CL = 50 pF
Min (n0+n1)Tc - 10 Tc (n0+n1)Tc - 10 -5 (n0+n1)Tc - 10 -5 n0Tc - 10 n1Tc - 10 40 0
Typ -- -- -- -- -- -- -- -- -- --
Max -- -- -- -- -- -- -- -- -- --
Units ns ns ns ns ns ns ns ns ns ns
n0 = address setup time, n1 = XOE_N/XWE_N pulse width, Tc = HCLK cycle Address setup time and XOE_N/XWE_N pulse width are parameters that can be set by the IOAC register.
tXIOCS IOCS_N/PIOC[5]
tXIOCSH1
tXIOAS XA[19:1]/PIOC[2:0] PIOB[15:0] tXIOBS XBS_N[1:0]/PIOC[9:8] tXIOBH1
tXIOAH1
XOE_N/PIOC[6]
tXIOOED
tXIOOEW
tXIODIS XD[15:0]/PIOA[15:0]
tXIODIH
Figure 6. External I/O Bus Read Cycle Timing
16 * Oki Semiconductor
ML675200/ML67Q5200
External I/O Bus Write Cycle [1]
(VDD_CORE = 1.65 V to 1.95 V, VDD_IO = 2.7 V to 3.6 V, TA = -30C to +70C) Parameter IOCS_N pulse width IOCS_N output hold time 2 XA[19:1] hold time 2 XBS_N[1:0] hold time 2 XWE_N output delay time XWE_N output delay time pulse width XD[15:0] output delay time XD[15:0] output hold time
1. 2.
Symbol tXIOCSW tXIOCSH2 tXIOAH2 tXIOBH2 tXIOWED tXIOWEW tXIODOD [2] tXIODOH
[2]
Condition CL = 50 pF
Min (n0+n1+1)Tc - 3 Tc -3 -3 n0Tc - 5 n1Tc - 3 -- Tc - 3
Typ -- -- -- -- -- -- -- --
Max -- -- -- -- -- -- n0Tc + 5 --
Units ns ns ns ns ns ns ns ns
n0 = address setup time, n1 = XOE_N/XWE_N pulse width, Tc = HCLK cycle Address setup time and XOE_N/XWE_N pulse width are parameters that can be set by the IOAC register. tXIODOD and tXIOWED are defined as a time period that starts from the point of change in IOCS_N, XA[19:0], or XBS_N[1:0], whichever signal changes last.
tXIOCSW tXIOCSH2 IOCS_N/PIOC[5]
tXIOAH2 XA[19:1]/PIOC[2:0] PIOB[15:0] tXIOBH2 XBS_N[1:0]/PIOC[9:8]
tXIOWED XWE_N/PIOC[7]
tXIOWEW
tXIODOD XD[15:0]/PIOA[15:0]
tXIODOH
Figure 7. External I/O Bus Write Cycle Timing
Oki Semiconductor * 17
ML675200/ML67Q5200
Synchronous Serial Interface Timing
The synchronous serial interface operate in master mode or slave mode. It also allows the user to set the polarity of the serial clock. When the polarity of the serial clock is set to positive, as shown in the figure below, transmit data (TXD) is driven on the falling edge of SIOCK. Receive data is sampled on the rising edge of SIOCK. Once the transmission/reception of the 8-bit data is completed, the clock stops at a high level, and the data output holds the last data. When the polarity of the serial clock is set to negative, transmit data is driven on the rising edge of SIOCK, and receive data is sampled on the falling edge of SIOCK. Once the transmission/reception of 8-bit data is completed, the clock stops at a low level, and the data output holds the last data.
Master Mode
Parameter Serial clock cycle Output data delay time Input data setup time Input data hold time T tMSSOD tMSSIS tMSSIH Symbol Condition CL = 50 pF Min 66.67 -- 40 0 Max -- 20 -- -- Units ns ns ns ns
T SIOCK[1] VH = 2.0 V VL = 0.8 V tMSSOD TXD
tMSSIS RXD 1. Indicates the case where the polarity of the serial clock is positive.
tMSSIH
Figure 8. Synchronous Serial Interface - Master Mode Timing
Slave Mode
Parameter Serial clock cycle Output data delay time Input data setup time Input data hold time T tSSSOD tSSSIS tSSSIH Symbol Condition CL = 50 pF Min 66.67 -- 20 20 Max -- 40 -- -- Units ns ns ns ns
T SIOCK[1] VH = 2.0 V VL = 0.8 V tSSSOD TXD
tSSSIS RXD 1. Indicates the case where the polarity of the serial clock is positive.
tSSSIH
Figure 9. Synchronous Serial Interface - Slave Mode Timing
18 * Oki Semiconductor
ML675200/ML67Q5200
I2C Bus Timing
Standard Mode Parameter SCL clock frequency SCL clock "L" period SCL clock "H" period Hold time (repetitive) "START" condition (After this period, the first clock pulse is generated.) Setup time for repetitive "START" condition Data hold time Data setup time Setup time for "STOP" condition
1.
Fast Mode Min -- 1.3 0.6 0.6 Max 400 -- -- -- Units kHz s s s
Symbol fSCL tLOW tHIGH tHD:STA
Min -- 4.7 4.0 4.0
Max 100 -- -- --
tSU:STA tHD:DAT tSU:DAT tSU:STO
4.7 5.0 250 4.0
-- -- -- --
0.6 -- 100
[1]
-- -- -- --
s s s s
0.6
Although I2C bus devices in Fast mode can be used in a standard I2C bus system, it is necessary to satisfy the required condition tSU:DAT 250 ns. This means that such devices do not automatically extend the "L" period of the SCL signal. If a device does not extend the "L" period of the SCL signal, the next data must be output to the SDA pin at least "trmax + tSU:DAT = 1000 + 250 = 1250 ns" (output the data bits that are in effect in the Standard mode according to the I2C Bus Specification) earlier than the time the SCL pin is opened
tSU:DAT PIOE[13]/SDAT tHD:S PIOE[14]/SCL
tLOW
tHD:DAT
tHIGH
tSU:STA
tHD:STA
tSU:STO
Figure 10. I2C Bus Timing
Oki Semiconductor * 19
ML675200/ML67Q5200
SAI Transceiver/Receiver Timing
Transceiver (for master only)
(VDD_CORE = 1.65 V to 1.95 V, VDD_IO = 2.7 V to 3.6 V, TA = -30C to +70C) Parameter Master clock frequency (256*fs) [1] Master clock frequency (384*fs) [1] Serial clock frequency Sampling frequency CKOUTD period (256*fs) CKOUTD period (384*fs) CKOUTD "L" period (256*fs) CKOUTD "L" period (384*fs) CKOUTD "H" period (256*fs) CKOUTD "H" period (384*fs) Serial clock period (fs = 44.1 KHz) SCLD "L" period (fs = 44.1 KHz) SCLD "H" period (fs = 44.1 KHz) WS output delay time Serial data (SDD) output delay time
1.
Symbol
Condition CL = 50 pF
Min. 2.0480 3.0720 --
Typ. 11.2896 16.9344 32*fs 44.1 88.6 59 44.3 29.5 44.3 29.5 708 354 354 -- --
Max. 12.2880 18.4320 -- 48 81.4 54.3 40.7 27.15 40.7 27.15 -- -- -- 50 50
Unit MHz MHz kHz kHz ns ns ns ns ns ns ns ns ns ns ns
Remarks Division ratio = 1/1, 1/2, 1/4 fs = 44.1, 32, 48 kHz
fs tT_MCLK tT_MCKL tT_MCKH tT_SCK tT_SCL tT_SCH tT_WSD tT_SDD
32 488 325 244 162.5 244 162.5 -- -- -- -- --
Typ.: fs = 1/1 division of 44.1 kHz, Min.: fs = 1/4 division of 32 kHz, Max.: fs = 1/1 division of 48 kHz
tT_MCLK tT_MCKH CKOUTD tT_MCKL VH = 2.0 V VL = 0.8 V tT_SCK WSD tT_SCK tT_SCH SCLD tT_SCL VH = 2.0 V VL = 0.8 V VH = 2.0 V VL = 0.8 V
WSD
tT_WSD SCLD VH = 2.0 V VL = 0.8 V tT_SDD SDD
Figure 11. SAI Transceiver Timing
20 * Oki Semiconductor
ML675200/ML67Q5200
Receiver (for master only)
(VDD_CORE = 1.65 V to 1.95 V, VDD_IO = 2.7 V to 3.6 V, TA = -30C to +70C) Parameter Master clock frequency (256*fs)
[1]
Symbol
Condition CL = 50 pF
Min. 2.0480 3.0720 --
Typ. 11.2896 16.9344 32*fs 44.1 88.6 59 44.3 29.5 44.3 29.5 708 354 354 --
Max. 12.2880 18.4320 -- 48 81.4 54.3 40.7 27.15 40.7 27.15 -- -- -- 50
Unit MHz MHz kHz kHz ns ns ns ns ns ns ns ns ns ns ns ns
Remarks Division ratio = 1/1, 1/2, 1/4 fs = 44.1, 32, 48 kHz
Master clock frequency (384*fs) [1] Serial clock frequency Sampling frequency CKOUTA period (256*fs) CKOUTA period (384*fs) CKOUTA "L" period (256*fs) CKOUTA "L" period (384*fs) CKOUTA "H" period (256*fs) CKOUTA "H" period (384*fs) Serial clock period (fs = 44.1 KHz) SCLA "L" period (fs = 44.1 KHz) SCLA "H" period (fs = 44.1 KHz) WS output delay time Serial data (SDA) setup time Serial data (SDA) hold time
1.
fs tR_MCLK tR_MCKL tR_MCKH tR_SCK tR_SCL tR_SCH tR_WSD tR_SDIS tR_SDIH
32 488 325 244 162.5 244 162.5 -- -- --
50 0
-- --
Typ.: fs = 1/1 division of 44.1 kHz, Min.: fs = 1/4 division of 32 kHz, Max.: fs = 1/1 division of 48 kHz
tR_MCLK tR_MCKH CKOUTA tR_MCKL VH = 2.0 V VL = 0.8 V tR_SCKK WSA tR_SCK tR_SCH SCLA tR_SCL VH = 2.0 V VL = 0.8 V VH = 2.0 V VL = 0.8 V
WSA
tR_WSA SCLA
tR_SDIS SDA
tR_SDIH
Figure 12. SAI Receiver Timing
Oki Semiconductor * 21
ML675200/ML67Q5200
NAND Flash Interface [1]
(VDD_CORE = 1.65 V to 1.95 V, VDD_IO = 2.7 V to 3.6 V, TA = -30C to +70C) Parameter FWR_N pulse width FWR_N "H" output hold time Data (FD[7:0]) setup time Data (FD[7:0]) hold time FRD_N pulse width FRD_N "H" output hold time FRD_N access time Data output hold time (FRD_N)
1.
Symbol tFWP tFWH tFDS tFDH tFRP tFREH tFREA tFRHZ
Condition CL = 50 pF
Min. (0.5*w1 + 1)Tc - 10 (0.5*w1 + 1)Tc - 10 w2*Tc - 20 w3*Tc - 10 r1*Tc - 10 r2*Tc - 10 r1*Tc - 20 0
Max. -- (0.5*w1 + 1)Tc +10 -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns
Tc = HCLK cycle To calculate, use the following w1, w2, and w3 values during sequencer write and the following r1 and r2 values during sequencer read: w1: 0 for "no write wait" mode; 1 for "1 write wait" mode; 2 for "2 write wait" mode w2: 1.5 for "no write wait" mode; 2 for "1 write wait" mode; 3 for "2 write wait" mode w3: 0.5 for "no write wait" mode; 1 for "1 write wait" mode; 1 for "2 write wait" mode r1: 1.5 for "no read wait" mode; 2 for "1 read wait" mode; 3 for "2 read wait" mode r2: 0.5 for "no read wait" mode; 1 for "1 read wait" mode; 1 for "2 read wait" mode
tFWP PIOE[9]/FWR_N
tFWH
tFWP
tFDS PIOE[7:0]/FD[7:0]
tFDH
tFDS
tFDH
Figure 13. Write Transfer
tFRP PIOE[8]/FRD_N
tFREH
tFREA PIOE[7:0]/FD[7:0]
tFRHZ
tFREA
tFRHZ
Figure 14. Read Transfer
22 * Oki Semiconductor
ML675200/ML67Q5200
USB Pins
USB - DC characteristics
(VBUS = 3.0 V to 3.6 V, VDD_CORE = 1.65 V to 1.95 V, TA = -30C to +70C) Parameter Differential input sensitivity Differential common mode range Single-ended receiver threshold voltage "H" output voltage Symbol VDI VCM VSE VOH Condition |(D+) - (D-)| VDI included -- 15 k to GND IOH = -100 A IOH = -4 mA "L" output voltage VOL 1.5 k to 3.6 V IOL = 100 A IOL= 4 mA Output leakage current IOZH IOZL VOH = VBUS VOL = 0 V Min. 0.2 0.8 0.8 2.8 VBUS - 0.2 2.4 -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- Max. -- 2.5 2 -- -- -- 0.3 0.2 0.4 10 10 A D+, DV V D+, DPUCTL V D+, DPUCTL Unit V Applied pin D+, D-
USB - AC characteristics
(VBUS = 3.0 V to 3.6 V, VDD_CORE = 1.65 V to 1.95 V, TA = -30C to +70C) Parameter Rise time Fall time Rise/fall time ratio Output signal crossover voltage Driver output resistance Symbol Tr Tf TRFM VCRS ZDRV Condition CL = 50 pF CL = 50 pF (TR/TF) -- During steady-state driving Min. 4 4 90 1.3 28 Typ -- -- -- -- -- Max. 20 20 111.11 2 44 Unit ns ns % V Applied pin D+, D-
USB - ADC Characteristics
Parameter Resolution Linearity error Differential linearity error Zero scale error Full scale error Conversion time Symbol n INL DNL Efs Ezs Tconv Condition Analog input source impedance Ri < 5 k Min. -- -- -- -- -- 6.7 Typ. -- 0.5 0.5 +2 -2 -- Max. 8 -- -- -- -- 26.7 Unit bit LSB LSB LSB LSB s per 1 channel Remarks
ML675200 3.3 V 0.1 F Analog Input + 10 F AIN[3:0] AGND VDD_CORE GND 0.1 F 10 F 0V AVDD VDD_IO 0.1 F 10 F 1.8 V 3.3 V
Figure 15. A/D External Filter Circuit
Oki Semiconductor * 23
ML675200/ML67Q5200
ML675200 Analog Input + 5 k 0.1 F AIN0 AIN1 AIN2 AIN3 Analog Input + 5 k 0.1 F
ML675200 AIN0 AIN1 AIN2 AIN3
VREF or AGND
Crosstalk is the difference between the A/D conversion results when the same analog input is applied to AIN0 through AIN3 (right side of figure) and the A/D conversion results of the circuit on the left.
Figure 16. Crosstalk Measurements
JTAG Pins (ARM Side, Teak DSP Side)
AC characteristics
(VBUS = 3.0 V to 3.6 V, VDD_CORE = 1.65 V to 1.95 V, TA = -30C to +70C) Parameter nTRST input pulse width TCK maximum frequency TDI input setup time TDI input hold time TMS input setup time TMS input hold time TDO output delay time TINTP output delay time Symbol fW_NTRST tTCK tS_TDI tH_TDI tS_TMS tH_TMS tD_TDO tD_TINT Condition CL = 50 pF Min. -- -- 25 25 25 25 -- -- Typ. -- -- -- -- -- -- -- -- Max. 1 5 -- -- -- -- 100 100 Unit s MHz ns ns ns ns ns ns TDOA, TDOT TINTP TMSA, TMST Applied pin NTRSTA TCKA, TCKT TDIA, TDIT
24 * Oki Semiconductor
ML675200/ML67Q5200
Development Environment
* SDT2.51 ARM Software Development Toolkit (C Compiler, C Linker, Assembler) * Oki ADI board Interface board for device having the same interface as ARM Multi-ICE. Oki is selling it under license from ARM. * ML675200 SDK (Under Development) Digital audio player software development kit (Sample software and board etc.)
Oki Semiconductor * 25
ML675200/ML67Q5200
Package Dimensions
Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before performing reflow mounting, contact the responsible Oki sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
Figure 17. P-LFBGA144-1111-0.80
26 * Oki Semiconductor
ML675200/ML67Q5200
Related Oki Documents for the ML675200/Q5200 [1]
Document ML675200 User's Manual
1. Available on the Oki Semiconductor web site www.okisemi.com/us.
Date April, 2003
Oki Semiconductor * 27
ML675200/ML67Q5200
Notice
The information contained herein can change without notice owing to product and/ or technical improvements. Please make sure before using the product that the information you are referring to is up-to-date. The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in the actual circuit and assembly designs. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with the use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges, including but not limited to operating voltage, power dissipation, and operating temperature. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including life support and maintenance. Certain parts in this document may need governmental approval before they can be exported to certain countries. The purchaser assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their own expense, for export to another country. Oki Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished by Oki Semiconductor in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Oki Semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Oki. Trademarks: Plat is a trademark of Oki Semiconductor. ARM, ARM7TDMI, and the ARM Powered Logo are registered trademarks, and AMBA, ARM7, and Multi-ICE are trademarks of Advanced RISC Machines, Ltd. Copyright 2003 Oki Semiconductor
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